1. Field of the Invention
The present invention relates to a priority selection circuit, and more particularly to a priority selection circuit to be used for interruption acceptance circuits, bus arbitration circuits and others.
2. Description of the Prior Art
FIG. 8 shows an arrangement of a priority selection circuit generally used for conventional interruption acceptance circuits and others and FIG. 9 is a circuit diagram showing the priority selection circuit in detail. In FIG. 8, blocks 1a to 1d are circuits having the same arrangement and same function, 2a to 2d respectively represent service request input terminals which input service requests for devices different from each other, and 3 designates an output terminal for outputting an address value indicative of one of devices such as input/output devices (not shown) corresponding to (connecting with) the circuits 1a to 1d. Further, numeral 4 denotes an input terminal for inputting the initial value of the address value indicative of the aforementioned device, which input terminal is grounded to input "the address value "0" indicating that all the aforementioned devices do not request the services. Numeral 5 depicts an input terminal for inputting the initial value of a priority level, which input terminal is connected to a ground connection to input the lowest priority level value "0" (although in FIG. 9 the input terminals 4, 5 and the output terminal 3 are indicated by one line, in practice a plurality of lines are provided because the priority level is pluralized). Moreover, 9a to 9d are comparators for comparison in the priority, i.e., the priority level value, of the aforementioned device with each of the corresponding circuits 1a to 1d. References 12a to 12d designate constant registers for storing the address values of the corresponding devices, and 70a to 70d denote registers for storing the priority levels thereof. Further, 31a to 31d are switching circuits for selecting the greatest value of the priority level values of the circuits 1a to 1d. The device corresponding to the circuits 1a to 1d having the greatest priority level value becomes the device having the highest priority. FIG. 9 shows the switching circuits 31a to 31d in detail where only the circuit arrangement of the circuit 1b is illustrated because the circuits 1a to 1d have the same arrangement and the same function.
In FIG. 9, 6b represents a flag (F) which takes a logic "1" signal when a service request is inputted from the service request input terminal 2b. The register 70b is a register (LVL) in which the priority level of the device connected to the service request input terminal 2b is written as described above. Numeral 8 designates an input terminal for the priority level value from the circuit 1a. One input of the comparator 9b is coupled to the output of the register 70b and the other input thereof is coupled to the input terminal 8 so that the comparator 9b outputs a logic "1" signal when the value of the output of the 70b is greater than the value of the input terminal 8. Further, 10b denotes an AND gate whose one input is connected to the output of the flag (F) 6b and whose other input is connected to the output of the comparator 9b. The AND gate 10b outputs a logical product of these two input signals. Numeral 11 depicts an input terminal for the address value indicative of the device from the circuit 1d. The address value corresponding to the device connected to the service request input terminal 2b is always read out from the constant register 12b. References 13b and 14b are transfer gates which are energized when the AND gate 10b outputs the logic "1". The input of the transfer gate 13b is coupled to the output of the register 70b and the input of the transfer gate 14b is coupled to the output of the constant register 12b. Reference 15b represents a NOT gate whose input is coupled to the output of the AND gate 10b. Further, 16b and 17b are transfer gates energized when the NOT gate 15b outputs the logic "1". The input of the transfer gate 16b is connected to the input terminal 8 and the input of the transfer gate 17b is connected to the input terminal 11. Numeral 18 is an output terminal for the priority level value of the circuit 1b to the circuit 1c which output terminal is coupled to the outputs of the transfer gate 13b and the transfer gate 16b. Moreover, numeral 19 is an output terminal for the device address value of the circuit 1b to the circuit 1c which output terminal is connected to the outputs of the transfer gates 14b and 17b.
Secondly, a description will be made hereinbelow with reference to FIGS. 8 and 9 in terms of the operation of the conventional priority selection circuit. The description of the entire circuit will first be made with reference to FIG. 8 and the detailed description will subsequently be made with reference to FIG. 9. Let it be assumed that the priority level values corresponding to the respective devices are written in the circuits 1a to 1d, for example, the value "2" is written in the register 70a of the circuit 1a, the value "1" is written in the register 70b, the value "0" is written in the register 70c of the circuit 1c and the value "2" is written in the register 70d of the circuit 1d (these values are shown in the register indicating blocks in FIG. 8). Further, let it be assumed that the address values different from each other and indicative of the respective devices corresponding to the circuits 1a to 1d are always read out from the constant registers 12a to 12d of the circuits 1a to 1d. In response to inputs of the service requests for the devices connected to the service request input terminals 2a, 2b and 2d, in the circuit 1a, the initial value "0" of the priority level inputted from the input terminal 5 and the priority level value "2" written in the register 70a of the circuit 1a are compared with each other in the comparator 9a. In this case, since the priority level value written in the register 70a is greater and the service request is made from the service request input terminal 2a, in the circuit 1a the priority level value "2" and the address value indicative of the device connected to the service request input terminal 2a are outputted through the switching circuit 31a to the circuit 1b. In the circuit 1b, the priority level value "2" supplied is compared with the priority level value "1" of the register 70b. In this case, since the priority level value from the circuit 1a is greater, irrespective of the service request to the service request input terminal 2b, the circuit 1b directly outputs the supplied priority level value "2" and the address value indicative of the device connected to the service request input terminal 2a. In the circuit 1c, since the service request is not made with respect to the service request input terminal 2c, regardless of the comparison in the priority level, the priority level value "2" supplied from the circuit 1b and the address value indicative of the device connected to the service request input terminal 2a are directly outputted to the circuit 1d. In the circuit 1d, the priority level value "2" supplied and the priority level value "2" written in the register 70d of the circuit 1d are compared with each other in the comparator 9d. In this case, since the priority level value "2" supplied from the circuit 1c is equal to the priority level value "2" of the register 70d, regardless of the service request to the service request input terminal 2d, in the circuit 1d the supplied address value indicative of the device connected to the service request input terminal 2a is directly outputted from the output terminal 3. With the aforementioned operation, the conventional priority selection circuit selects, of the service-requested devices, the device having the highest priority level, i.e., the device having the greatest priority level value, or the device having the same value.
Further, the operation of the circuit 1b will be described hereinbelow with reference to FIG. 9 in terms of the case the circuit 1b is responsive to the priority level value "2" from the circuit 1a to output this value "2" to the circuit 1c as described above. In response to input of the service request from the service request input terminal 2b, the flag 6b is set to output the logic "1", whereby one input of the AND gate 10b becomes the logic "1". On the other hand, the comparator 9b always compares the priority level value "0" outputted from the register 70b with the priority level value "2" inputted from the input terminal 8. Only in the case that the priority level value of the register 70b is greater than the priority level value inputted from the input terminal 8, the comparator 9b outputs the logic "1". Since the output of the comparator 9b is the other input of the AND gate 10b, the output of the AND gate 10b becomes the logic "1" only in the case that the service request is inputted from the service request input terminal 2b and the priority level value of the register 70b is higher than the priority level value from the input terminal 8. In the other cases, that is, in the case of no service request, and in the case that, although the service request is made, the priority level value of the register 70b is equal to the priority level value from the input terminal 8 or lower than the priority level value therefrom, the logic "0" is outputted. Thus, in this case, the comparator 9b outputs the logic "0". In the case that the output of the AND gate 10b is the logic "1", the output of the NOT gate 15b becomes the logic "0", and in the case that the output of the AND gate 10b is the logic "0", the output of the NOT gate 15b becomes "1". Further, in the case that the output of the AND gate 10b is the logic "1", the transfer gates 13 and 14 takes the energized state, and in the case that the output of the AND gate 10b is the logic "0", the transfer gates 16 and 17 takes the energized state.
As described above, in the circuit 1b, the logic "0" signal is outputted from the comparator 9b so that the output of the AND gate becomes the logic "0" and inverted by the NOT gate 15b before outputted. As a result, the transfer gates 16b and 17b take the energized states and the transfer gates 13b and 14b take the OFF states, and the priority level value "2" from the circuit 1a and the address value indicative of the device corresponding to the circuit 1a are outputted to the circuit 1c. Accordingly, only in the case that the service request is inputted and the priority level value of the register 70b is higher than the priority level value from the input terminal 8, the priority level value of the register 70b is outputted through the output terminal 18 and the device address value of the constant register 12b is outputted through the output terminal 19. In the other cases, the priority level from the input terminal 8 is outputted through the output terminal 18 and the address value from the input terminal 11 is outputted through the output terminal 19.
Since the conventional priority selection circuit is arranged as described above, in the case that, for example, the service requests for the devices having high priority levels are successively inputted, there is a problem that difficulty is encountered to accept the service requests for the devices having low priority levels because of accepting only the service requests for the devices having the high priority levels.